The present invention relates generally to reducing the amount of power consumed by an integrated circuit and more particularly to reducing the standby power consumed by a dynamic random access memory (DRAM).
A typical DRAM memory device is comprised of a plurality of memory cells, each comprised of a transistor and a capacitor. Each memory cell stores one bit of data in the form of a voltage. A high voltage level (e.g., 3V) represents a logic “1”, whereas a low voltage level (e.g., 0V) represents a logic “0”. The memory cells may be arranged in an array with each memory cell being connected to a wordline and a digitline. The DRAM may also include peripheral devices, such as drivers, sense amps, input/output devices, and power supplies, etc., that are used to identify memory cells, access the memory cells, and store information within and read information from the memory cells, among others.
One characteristic associated with DRAMs is that the voltage stored on the capacitors of the individual cells tend to dissipate over time as a result of leakage currents. Thus, the cells of the DRAM must be periodically refreshed to ensure the integrity of the data stored therein. A refresh operation generally comprises sensing the data held in certain of the memory cells and then restoring the data from the sense amplifiers back to full CMOS logic levels in the memory cells. The maximum amount of time that may pass before a refresh operation must be completed (i.e., before the memory cells lose their stored charge) is referred to as the refresh rate. Due to their structure, DRAM's may have multiple refresh rates depending of their mode of operation. For example, a DRAM operating in the standby mode (e.g., when the digitlines are equalized and precharged to Vcc/2 and the wordlines are off) may have one refresh rate, referred to as a “static refresh rate,” whereas the same DRAM operating in the active mode (e.g., when the sense amps are active and the digitlines are forced to CMOS logic levels (Vcc and GND)) may have another refresh rate, referred to as a “dynamic refresh rate.”
The amount of stand-by power or “self-refresh” current used by the DRAM is dependent upon the refresh rate. Stand-by power and self-refresh current can be reduced by refreshing at the DRAM's slowest possible refresh rate. For example, a pseudo-static random access memory (PSRAM) may have a static refresh rate of approximately 1000 mS (i.e., the cells need refreshing every 1000 mS), and a dynamic refresh rate of approximately 100 mS (i.e., cells need refreshing every 100 mS). Refreshing the PSRAM every 1000 mS (i.e., at the static refresh rate), as compared to refreshing the PSRAM every 100 mS (i.e., the dynamic refresh rate), will consume less stand-by power and self-refresh current because the refresh operations are executed less often. However, since the DRAM memory array must operate both in standby and active modes, the faster dynamic refresh rate sets the overall refresh rate of the device. Thus, the refresh rate is set at the worst case condition (here, the 100 mS refresh rate) to insure the integrity of the stored data.
Thus, there exists a need for an apparatus and method for taking advantage of the longer available refresh rate, thereby reducing current flow in a memory device during the standby mode and overcoming other limitations inherent in prior art.